1. Field of the Invention
The present invention relates to an address transition detection circuit for a memory device, and more particularly to an address transition detection circuit in which an address transition detect signal having a pulse width required for operating the memory, device is outputted regardless of a pulse width of an address signal inputted to the memory, device to thereby prevent any malfunction of the memory device.
2. Description of the Prior Art
A conventional address transition detection circuit for a memory device, referring to FIG. 1, includes a NOR gate 1 for NORing an input chip select signal CSb and an input address signal AD: a latch 2 for latching the signal provided from the NOR gate 1 and outputting inverted latch signals LS1 and LS2; signal delays 3 and 4 for delaying the latch signals LS1 and LS2 provided from the latch 2 for a predetermined time and outputting delayed signals DLS1 and DLS2; and a signal outputting unit 5 for outputting an address transition detect signal ATDS in response to the latch signal LS1 and LS2 provided from the latch 2 and the delay signals DLS1 and DLS2 respectively provided from the signal delays 3 and 4.
The latch 2 includes a NAND gate 22 for NANDing both the signal provided from the NOR gate 1 and inverted through an inverter 21 and an input signal LS2 to output the latch signal LS1, and also a NAND gate 23 for NANDing the signals respectively provided from both the NOR gate 1 and the signal LS1 from the NAND gate 22 to output the latch signal LS2.
The signal delay 3 includes inverters 31 and 32 for sequentially inverting the latch signal LS1 provided from the latch 2, and the signal delay 4 includes inverters 41 and 42 for sequentially inverting the latch signal LS2 provided from the latch 2.
The signal outputting unit 5 includes a PMOS transistor MP1 having a source to which a power supply voltage VCC is applied and a gate to which the delayed signal line DLS1 from the signal delay 3 is applied; a PMOS transistor MP2 having a source to which the drain of the PMOS transistor MP1 is connected and a gate to which the latch signal LS1 from the latch 2 is applied and a drain connected to an address transition detect signal ATDS output line; an NMOS transistor MN1 having its drain connected in common with the drain of PMOS transistor MP2, and also having its gate connected in common with the gate of PMOS transistor MP2; an NMOS transistor MN2 having a drain to which a source of the NMOS transistor MN1 is connected, a gate to which the delay signal DLS2 from the signal delay 4 is applied, and a source connected to ground; a PMOS transistor MP3 having a source to which the power supply voltage VCC is applied, a gate to which the gate of the NMOS transistor MN2 is connected; a PMOS transistor MP4 having a source to which a drain of the PMOS transistor MP3 is connected, a gate to which the latch signal LS2 from the latch 2 is applied and a drain connected to the address transition detect signal ATDS output line; an NMOS transistor MN3 having its drain connected in common with the drain of PMOS transistor MP4 and also having its gate connected in common with the gate of PMOS transistor MP4; and an NMOS transistor NM4 having a drain to which a source of the NMOS transistor MN3 is connected, a gate to which the gate of the PMOS transistor MP1 is connected, and a source connected to ground.
The operation of the conventional address transition detection circuit for a memory device as constructed above will now be described.
At an initial stage, when a low level chip select signal CSb and a low level address signal AD are inputted, the NOR gate 1 outputs a high level signal after NORing the inputted signals CSb and AD.
Then, the NAND gate 22 of the latch 2 receives at one input terminal thereof the signal provided from the NOR gate 1 and inverted as a low level signal through the inverter 21, and outputs a high level latch signal LS1 regardless of a state of the signal provided from the NAND gate 23 and applied to the other input terminal thereof.
The NAND gate 23 receives at one input terminal thereof the high level signal provided from the NOR gate 1 and at the other input terminal thereof the high level latch signal LS1 provided from the NAND gate 22, NANDing the high level signal and the high level latch signal LS1, to output a low level latch signal LS2.
The high level latch signal LS1 provided from the NAND gate 22 is delayed for a predetermined time by sequentially passing through the inverters 31 and 32 of the delay 3 so as to be outputted as a high level delay signal DLS1, while the low level latch signal LS2 provided from the NAND gate 23 is delayed for a predetermined time by sequentially passing through the inverters 41 and 42 of the delay 4 so as to be outputted as a low level delay signal DLS2.
Then, the PMOS transistor MP1 and the NMOS transistor MN4 of the signal output unit 5 receive the high level signal DLS1 provided sequentially through the inverters 31 and 32 so as to be turned off and turned on, respectively, while the PMOS transistor MP2 and the NMOS transistor MN1 commonly receive at each gate thereof the high level latch signal LS1 provided from the NAND gate 22 so as to be turned off and turned on, respectively.
In the meantime, the NMOS transistor MN2 and the PMOS transistor MP3 receive at each gate thereof the low level signal DLS2 provided sequentially through the inverters 41 and 42 so as to be turned off and turned on, respectively, while the PMOS transistor MP4 and the NMOS transistor MN3 commonly receive at each gate thereof the low level latch signal LS2 provided from the NAND gate 23 so as to be turned on and turned off, respectively.
Accordingly, a high level address transition detect signal ATDS is outputted through the address transition detect signal ATDS output line.
Thereafter, under the condition that a low level address signal AD is transitted to a high level address signal AD, when a pulse width of the address signal AD transitted to the high level signal is longer than a pulse width of an address transition detect signal required for operating the memory device, the high level address signal AD having the pulse width is inputted, with which when a low level chip select signal CSb is inputted, the NOR gate 1 outputs a low level signal by NORing the inputted signals CSb and AD.
Then, the NAND gate 23 receives at one input terminal thereof the low level signal provided from the NOR gate 1, NANDing it with the high level signal LS1 applied to the other input terminal thereof, to output a high level signal LS2, while the NAND gate 22 receives at one input terminal thereof the high level signal inverted through the inverter 21 and at the other input terminal thereof the high level signal LS2 provided from the NAND gate 23, NANDing the high level signals, to output a low level signal LS1.
Accordingly the PMOS transistor MP2 and the NMOS transistor MN1 commonly receive at each gate thereof the low level signal LS1 provided from the NAND gate 22 so as to be turned on and turned off, respectively, while the PMOS transistor MP4 and the NMOS transistor MN3 commonly receive at each gate thereof the high level signal LS2 provided from the NAND gate 23 so as to be turned off and turned on, respectively.
And, the PMOS transistors MP1 and MP3 and the NMOS transistors MN2 and MN4 are maintained at their immediately preceding switched conditions until the signals LS1 and LS2 respectively provided from the NAND gates 22 and 23 are outputted after passing the delays 3 and 4, so that the high level signal ATDS being provided through the address transition detect signal ATDS output line is transitted to be outputted as a low level signal.
Thereafter, when a low level signal DLS1 is outputted sequentially through the inverters 31 and 32 and a high level signal DLS2 is outputted through the inverters 41 and 42, the PMOS transistor MP1 and the NMOS transistor MN4 receive at each gate thereof the output low level signal DLS1 so as to be turned on and turned off, respectively, while the NMOS transistor MN2 and the PMOS transistor MP3 receive at each gate thereof the outputted high level signal DLS2 so as to be turned on and turned off, respectively.
Since the PMOS transistors MP2 and MP4 and the NMOS transistors MN1 and MN3 are maintained at their immediately preceding switched conditions, the low level address transition detect signal ATDS being provided through the address transition detect signal ATDS output line is transitted to a high level signal to be outputted.
Thereafter, when the high level address signal AD is transitted to the low level address signal AD to be inputted and the low level chip select signal CSb is inputted, the NOR gate 1 outputs a high level signal after NORing the inputted signals AD and CSb.
Then, the NAND gate 23 receives at one input terminal thereof the high level signal provided from the NOR gate 1, NANDing it with the low level signal LS1 applied to the other input terminal thereof, to output a high level signal LS2, while the NAND gate 22 receives at one input terminal thereof the low level signal inverted through the invertor 21 and at the other input terminal thereof the high level signal LS2 provided from the NAND gate 23, NANDing the low level signal and the high level signal LS2, to output a high level signal LS1.
Accordingly, the NAND gate 23 receives at the other input terminal thereof the high level signal LS1 from the NAND gate 22, NANDing it with the high level signal applied to one input terminal thereof, to output a low level signal LS2.
Therefore, the PMOS transistor MP2 and the NMOS transistor MN1 commonly receive at each gate thereof the high level signal LS1 provided from the NAND gate 22 so as to be turned on and turned off, respectively, while the PMOS transistor MP4 and the NMOS transistor MN3 commonly receive at each gate thereof the low level signal LS2 provided from the NAND gate 23 so as to be turned on and turned off, respectively.
And, since the PMOS transistors MP1 and MP3 and the NMOS transistors MN2 and MN4 are maintained at their immediately preceding switched conditions until the signals LS1 and LS2 respectively provided from the NAND gates 22 and 23 are outputted, respectively, the high level address transition detect signal ATDS being provided through the address transition detect signal ATDS output fine is transitted to be outputted as a low level address transition detect signal ATDS.
Thereafter, when the high level signal LS1 provided from the NAND gate 22 is delayed for a predetermined time after sequentially passing through the inverters 31 and 32 to be outputted as a high level signal DLS1 and a low level signal LS2 provided from the NAND gate 23 is delayed for a predetermined time after sequentially passing through the inverters 41 and 42 to be outputted as a low level signal DLS2, the PMOS transistor MP1 and the NMOS transistor MN4 receive at each gate thereof the high level signal DLS1 provided from the inverter 32 so as to be turned on and turned off, respectively, while the NMOS transistor MN2 and the PMOS transistor MP3 receive at each gate thereof the low level signal DLS2 provided from the inverter 42 so as to be turned off and turned on, respectively.
Since the PMOS transistors MP2 and MP1 and the NMOS transistors MN1 and MN3 are maintained at their immediately preceding switched conditions, the low level address transition detect signal ATDS provided through the address transition detect signal ATDS output line is transitted to a high level address transition detect signal to be outputted.
Consequently, when the address signal AD is transitted from a low level signal to a high level signal, the pulse width of the address transition detect signal ATDS is determined according to the delay time of the signal delay 3, while when the address signal AD is transitted from a low level to a high level, the pulse width of the address transition detect signal ATDS is determined according to the delay time of the signal delay 4.
In the meantime, when the address signal AD having a pulse width shorter than that of the high level address transition detect signal ATDS required for operating the memory device is inputted and the low level chip select signal CSb is also inputted, the address transition detection circuit is operated in the same manner as described above, so that a low level address transition detect signal ATDS is outputted through the address transition detect signal ATDS output line which has a pulse width shorter than that of the address transition detect signal required for operating the memory device.
However, in the conventional address transition detection circuit for the memory device, when an address signal is inputted having a pulse width shorter than that according to a delay time of a signal delay, that is, a pulse width shorter than that of the address transition detect signal required for operating the memory device, an address transition detect signal having the same pulse width as that of the inputted address signal is outputted to the memory device, causing a problem that an operation of the memory device is rendered unstable and unreliable.